? semiconductor components industries, llc, 2015 march, 2015 ? rev. 1 1 publication order number: ncp120/d ncp120 150ma, very low dropout bias rail cmos voltage regulator the ncp120 is a 150 ma vldo equipped with nmos pass transistor and a separate bias supply voltage (v bias ). the device provides very stable, accurate output voltage with low noise suitable for space constrained, noise sensitive applications. in order to optimize performance for battery operated portable applications, the ncp120 features low i q consumption. the xdfn6 1.2 mm x 1.2 mm package is optimized for use in space constrained applications. features ? input voltage range: 0.8 v to 5.5 v ? bias voltage range: 2.4 v to 5.5 v ? fixed output voltage device ? output voltage range: 0.8 v to 2.1 v ? 1.5% accuracy over temperature, 0.5% v out @ 25 c ? ultra?low dropout: 75 mv maximum at 150 ma ? very low bias input current of typ. 80 a ? very low bias input current in disable mode: typ. 0.5 a ? logic level enable input for on/off control ? output active discharge option available ? stable with a 1 f ceramic capacitor ? available in xdfn6 ? 1.2 mm x 1.2 mm x 0.4 mm package ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? battery?powered equipment ? smartphones, tablets ? cameras, dvrs, stb and camcorders bias in en out gnd 1 f v out 1.05 v @ 150 ma v bias 2.7 v v in 1.2 v v en 1 f 100 nf ncp120 figure 1. typical application schematics www. onsemi.com see detailed ordering, marking and shipping information on page 7 of this data sheet. ordering information marking diagram pin connections thermal t pad 1 2 3 6 5 4 out nc en in gnd bias (top view) xdfn6 case 711at x m x = specific device code m = date code
ncp120 www. onsemi.com 2 en current limit thermal limit uvlo + ? voltage reference in bias gnd out *active discharge enable block *active output discharge function is present only in ncp120amxyyytcg devices. yyy denotes the particular output voltage option. figure 2. simplified schematic block diagram 150 pin function description pin no. pin name description 1 out regulated output voltage pin 2 n/c not internally connected 3 en enable pin. driving this pin high enables the regulator. dr iving this pin low puts the regulator into shutdown mode. 4 bias bias voltage supply for internal control circuits. this pi n is monitored by internal under-voltage lockout circuit. 5 gnd ground pin 6 in input voltage supply pin pad should be soldered to the ground plane for increased thermal performance. absolute maximum ratings rating symbol value unit input voltage (note 1) v in ?0.3 to 6 v output voltage v out ?0.3 to (v in +0.3) 6 v chip enable and bias input v en, v bias ?0.3 to 6 v output short circuit duration t sc unlimited s maximum junction temperature t j 150 c storage temperature t stg ?55 to 150 c esd capability, human body model (note 2) esd hbm 2000 v esd capability, machine model (note 2) esd mm 200 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. refer to electrical characteristis and application information for safe operating area. 2. this device series incorporates esd protection (except out pin) and is tested by the following methods: esd human body model tested per eia/jesd22?a114 esd machine model tested per eia/jesd22?a115 latchup current maximum rating tested per jedec standard: jesd78. thermal characteristics rating symbol value unit thermal characteristics, xdfn6 1.2 mm x 1.2 mm thermal resistance, junction?to?air r ja 170 c/w
ncp120 www. onsemi.com 3 electrical characteristics ?40 c t j 85 c; v bias = 2.7 v or (v out + 1.6 v), whichever is greater, v in = v out(nom) + 0.3 v, i out = 1 ma, v en = 1 v, unless otherwise noted. c in = 1 f, c bias = 0.1 f, c out = 1 f (effective capacitance) (note 3). typical values are at t j = +25 c. min/max values are for ?40 c t j 85 c unless otherwise noted. (note 4) parameter test conditions symbol min typ max unit operating input voltage range v in v out +v do 5.5 v operating bias voltage range v bias (v out +1.35) 2.4 5.5 v undervoltage lock?out v bias rising hysteresis uvlo 1.6 0.2 v output voltage accuracy ?40 c t j 85 c, v out(nom) + 0.3 v v in 5.0 v, 2.7 v or (v out(nom) + 1.6 v), whichever is greater < v bias < 5.5 v, 1 ma < i out < 150 ma v out ?1.5 +1.5 % output voltage accuracy v out 0.5 % v in line regulation v out(nom) + 0.3 v v in 5.0 v line reg 0.01 %/v v bias line regulation 2.7 v or (v out(nom) + 1.6 v), whichever is greater < v bias < 5.5 v line reg 0.01 %/v load regulation i out = 1 ma to 150 ma load reg 1.5 mv v in dropout voltage i out = 150 ma (note 5) v do 37 75 mv v bias dropout voltage i out = 150 ma, v in = v bias (note 5) v do 1.1 1.4 v output current limit v out = 90% v out(nom) i cl 200 330 600 ma bias pin operating current v bias = 2.7 v i bias 80 110 a bias pin disable current v en 0.4 v i bias(dis) 0.5 1 a vinput pin disable current v en 0.4 v i vin(dis) 0.5 1 a en pin threshold voltage en input voltage ?h? v en(h) 0.9 v en input voltage ?l? v en(l) 0.4 en pull down current v en = 5.5 v i en 0.3 1.0 a turn?on time c out = 1 f, from assertion of v en to v out = 98% v out(nom) , v out(nom) = 1.05 v t on 150 s power supply rejection ratio v in to v out , f = 1 khz, i out = 150 ma, v in v out +0.5 v psrr(v in ) 70 db v bias to v out , f = 1 khz, i out = 150 ma, v in v out +0.5 v psrr(v bias ) 80 db output noise voltage v in = v out +0.5 v, v out(nom) = 1.05 v, f = 10 hz to 100 khz v n 40 v rms thermal shutdown threshold temperature increasing 160 c temperature decreasing 140 output discharge pull?down v en 0.4 v, v out = 0.5 v, ncp120a options only r disch 150 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. effective capacitance, including the effect of dc bias, tolerance and temperature. see the application information section fo r more information. 4. performance guar anteed over the indicated operating temperature range by design and/or characterization. production tested at t a = 25 c. low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possibl e. 5. dropout voltage is characterized when v out falls 3% below v out(nom) .
ncp120 www. onsemi.com 4 applications information in en fb lx gnd processor i/o bias in out gnd ncp120 load vbat 2.6 v ? 4.2 v . 1.2 v 1.05 v to other circuits i/o en figure 3. typical application: low?voltage post?regulator with on/off functionality dc/dc 1.2 v v out(nom)
ncp120 www. onsemi.com 5 typical characteristics at t j = +25 c, v in = v out(typ) + 0.3 v, v bias = 2.7 v, v en = v bias , v out(nom) = 1.05 v, i out = 150 ma, c in = 1 f, c bias = 0.1 f, and c out = 1 f (effective capacitance), unless otherwise noted. figure 4. v in dropout voltage vs. i out and temperature t j figure 5. v in dropout voltage vs. (v bias ? v out ) and temperature t j i out , output current (ma) v bias ? v out (v) 100 0 0 10 20 30 40 50 60 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 20 40 80 100 v do (v in ? v out ) dropout voltage (mv) +125 c +25 c ?40 c 4. 5 60 120 +125 c +25 c ?40 c i out = 150 ma v do (v in ? v out ) dropout voltage (mv) figure 6. v bias dropout voltage vs. i out and temperature t j figure 7. bias pin current vs. i out and temperature t j i out , output current (ma) 100 0 800 900 1000 1100 1200 1300 1400 figure 8. bias pin current vs. v bias and temperature t j figure 9. current limit vs. (v bias ? v out ) i out , output current (ma) v bias (v) 100 0 0 20 60 80 120 140 5.0 4.5 4.0 5.5 3.5 3.0 2.5 2.0 0 20 60 80 100 140 180 200 i bias ( a) i bias ( a) v do (v bias ? v out ) dropout voltage (mv) +125 c +25 c ?40 c 40 100 +125 c +85 c ?40 c 40 120 160 +85 c 150 50 +85 c 150 50 +85 c +25 c 15 0 50 +125 c +85 c ?40 c +25 c v bias ? v out (v) 4.5 4.0 3.0 2.5 1.5 1.0 0.5 0 0 100 300 400 500 i cl , current limit (ma) +125 c +25 c ?40 c 2.0 3.5 5 .0 200 600 +85 c 160 180 140 200
ncp120 www. onsemi.com 6 applications information the ncp120 dual?rail very low dropout voltage regulator is using nmos pass transistor for output voltage regulation from v in voltage. all the low current internal controll circuitry is powered from the v bias voltage. the use of an nmos pass transistor offers several advantages in applications. unlike a pmos topology devices, the output capacitor has reduced impact on loop stability. v in to v out operating voltage difference can be very low compared with standard pmos regulators in very low v in applications. the ncp120 offers smooth monotonic start-up. the controlled voltage rising limits the inrush current. the enable (en) input is equipped with internal hysteresis. ncp120 is a fixed voltage linear regulator. dropout voltage because of two power supply inputs v in and v bias and one v out regulator output, there are two dropout voltages specified. the first, the v in dropout voltage is the voltage difference (v in ? v out ) when v out starts to decrease by percents specified in the electrical characteristics table. v bias is high enough, specific value is published in the electrical characteristics table. the second, v bias dropout voltage is the voltage difference (v bias ? v out ) when v in and v bias pins are joined together and v out starts to decrease. input and output capacitors the device is designed to be stable for ceramic output capacitors with ef fective capacitance in the range from 1 f to 10 f. the device is also stable with multiple capacitors in parallel, having the total effective capacitance in the specified range. in applications where no low input supplies impedance available (pcb inductance in v in and/or v bias inputs as example), the recommended c in = 1 f and c bias = 0.1 f or greater. ceramic capacitors are recommended . for the best performance all the capacitors should be connected to the ncp120 respective pins directly in the device pcb copper layer, not through vias having not negligible impedance. when using small ceramic capacitor, their capacitance is not constant but varies with applied dc biasing voltage, temperature and tolerance. the ef fective capacitance can be much lower than their nominal capacitance value, most importantly in negative temperatures and higher ldo output voltages. that is why the recommended output capacitor capacitance value is specified as effective value in the specific application conditions. enable operation the enable pin will turn the regulator on or off. the threshold limits are covered in the electrical characteristics table in this data sheet. if the enable function is not to be used then the pin should be connected to v in or v bias . current limitation the internal current limitation circuitry allows the device to supply the full nominal current and surges but protects the device against current overload or short. thermal protection internal thermal shutdown (tsd) circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. when tsd activated , the regulator output turns off. when cooling down under the low temperature threshold, device output is activated again. this tsd feature is provided to prevent failures from accidental overheating.
ncp120 www. onsemi.com 7 ordering information device nominal output voltage marking marking rotation option package shipping ? ncp120amx080tcg 0.80 v a 180 output active discharge xdfn6 (pb?free) 3000 / tape & reel ncp120amx105tcg 1.05 v d 180 ncp120amx110tcg 1.10 v e 180 ncp120amx115tcg 1.15 v f 180 ncp120amx120tcg 1.20 v j 180 ncp120amx150tcg 1.50 v k 180 ncp120amx180tcg 1.80 v l 180 ncp120amx210tcg 2.10 v p 180 ncp120bmx080tcg 0.80 v a 270 non?active discharge ncp120bmx105tcg 1.05 v d 270 NCP120BMX110TCG 1.10 v e 270 ncp120bmx115tcg 1.15 v f 270 ncp120bmx120tcg 1.20 v j 270 ncp120bmx150tcg 1.50 v k 270 ncp120bmx180tcg 1.80 v l 270 ncp120bmx210tcg 2.10 v p 270 ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging spe- cifications brochure, brd8011/d. to order other package and voltage variants, please contact your on sales representative
ncp120 www. onsemi.com 8 package dimensions xdfn6 1.20x1.20, 0.40p case 711at issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.25mm from terminal tips. 4. coplanarity applies to the pad as well as the terminals. a seating plane 0.05 c a a1 2x 2x 0.05 c dim a min max millimeters 0.30 0.45 a1 0.00 0.05 b 0.13 0.23 d e e l pin one reference 0.05 c 0.05 c note 3 l e b 3 6 6x 1 4 mounting footprint* 0.15 0.25 bottom view e2 dimensions: millimeters 0.35 6x 0.24 6x 1.40 0.40 pitch *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. e2 0.20 0.40 top view b side view note 4 recommended c 6x a m 0.10 b c package outline d2 0.84 1.04 l1 1.20 bsc 1.20 bsc 0.40 bsc 0.05 ref d2 1.08 0.40 d e detail b detail a detail a optional construction l ??? 1 l1 6x on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp120/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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